The VIC Cronicles Part 1

By Michael Doornbos

- 5 minutes read - 900 words

Recreating the VIC-20’s VIC Chip (6560) in an FPGA - Part 1

The Commodore VIC-20, released in 1980, was a groundbreaking home computer that brought personal computing to the masses. Central to its display capabilities was the VIC chip (Video Interface Chip), known as the 6560 in NTSC regions. In this multi-part series, we will explore the process of recreating the 6560 VIC chip using an FPGA. This first part covers an introduction to the VIC chip’s architecture, the basics of NTSC video, and the key challenges involved in the FPGA implementation.

Why Recreate the VIC-20 VIC Chip?

The VIC-20 is a beloved retro computer, and many enthusiasts still use or restore these systems today. Unfortunately, as with any vintage hardware, critical components like the VIC chip can fail or become unavailable. By creating an FPGA-based replacement, we can:

  • Restore non-functional VIC-20 systems
  • Preserve the VIC-20’s legacy by providing a long-term replacement and an open-source core for the chip

Overview of the VIC-20 VIC Chip (6560)

The 6560 VIC chip handles several key tasks in the VIC-20:

  1. Video output: It generates the video signal in NTSC or PAL format.
  2. Character rendering: It reads character data from memory and converts it into pixel data.
  3. Memory access: It shares access to the system’s memory with the 6502 CPU.

The VIC-20 displays 22 characters per row, each 8 pixels wide. The display resolution in text mode is typically 176x184 pixels, though the VIC chip also manages blanking areas and sync signals for video output.

NTSC Video Basics

Since the original VIC-20 used NTSC video output (for North American systems), understanding the NTSC standard is crucial for recreating the chip’s functionality.

Key NTSC Timing Details:

  • Horizontal scan rate: 15.734 kHz (63.5 microseconds per scanline).
  • Vertical refresh rate: ~60 Hz (approximately 262 scanlines per frame).
  • Pixel clock speed: The VIC chip effectively outputs pixels at 3.58 MHz (matching the NTSC color burst frequency).

The 6560 divides the 14.31818 MHz system clock by 4 to derive the pixel clock and by 14 to generate the 1.0227 MHz bus clock. This bus clock governs memory access and synchronizes with the 6502 CPU.

Understanding the Scanline Structure

Each NTSC scanline in the VIC-20 is broken down as follows:

  1. 228 total pixels per scanline: This includes both the visible pixels and blanking periods.
  2. Active video region: The 22 characters (176 pixels) occupy part of the scanline.
  3. Blanking and sync: The rest of the scanline includes horizontal sync signals.

A full scanline lasts 63.5 microseconds, during which the VIC outputs pixels and sends synchronization signals to the display.

Challenges in Recreating the 6560 in an FPGA

Recreating the VIC chip in an FPGA presents several challenges:

1. Video Signal Generation

We need to generate an accurate NTSC composite video signal or convert it to a modern output like HDMI or VGA while maintaining correct timing.

2. Memory Access Timing

The VIC-20’s shared memory architecture means that the VIC chip and the 6502 CPU must take turns accessing memory. Timing this correctly is crucial to ensure proper rendering of characters and graphics.

3. Character ROM and Graphics Data

The VIC chip reads character bitmaps from a built-in character ROM. For the FPGA implementation, we will need to load this ROM data and ensure that character rendering works as expected.

4. Clock Division and Synchronization

The FPGA must correctly divide the incoming 14.31818 MHz clock to derive the necessary pixel clock and bus clock, ensuring accurate video and memory access timing.

5. Expanding or Enhancing Output

While staying true to the original VIC chip, there is potential to add enhanced video output formats like VGA, RGB, or HDMI for better compatibility with modern displays.

Our Approach

In this series, we will break down the FPGA implementation into manageable steps:

  1. NTSC timing and video signal generation (Part 2)
  2. Memory interface and CPU coordination (Part 3)
  3. Character and bitmap rendering (Part 4)
  4. Clock division and internal synchronization (Part 5)
  5. Generating composite video (Part 6)
  6. Testing and debugging the FPGA implementation (Part 7)
  7. Adding modern display outputs (HDMI, VGA) (Part 8)
  8. Emulating VIC features and optional expansions (Part 9)
  9. Final testing and integration into a VIC-20 (Part 10)

Conclusion

This first part provided an overview of the VIC chip’s functionality and the challenges involved in recreating it using an FPGA. In the next part, we will dive into understanding NTSC video timing and generating the correct scanline structure in the FPGA.

Recreating a chip as iconic as the 6560 is both a technical challenge and an exciting opportunity to preserve and extend the life of the VIC-20. Stay tuned as we begin the detailed design and implementation!

Addendum: PAL Version Details

While this series focuses on recreating the NTSC version (6560) of the VIC chip, it is important to note the key differences for the PAL version (6561), commonly used in Europe:

  • System clock frequency: 14.1875 MHz instead of 14.31818 MHz.
  • Vertical refresh rate: ~50 Hz (compared to 60 Hz in NTSC systems).
  • Horizontal scan rate: Slightly lower than NTSC, at approximately 15.625 kHz.
  • Number of scanlines per frame: ~312 for PAL compared to 262 for NTSC.

The PAL version requires slightly different video timing and character rendering to accommodate the lower refresh rate and increased number of scanlines. Although this series will primarily address NTSC implementation, the final design can be adapted to support both formats by handling these differences in timing and configuration.