Video Timing Reference

Pixel clocks and porch-level horizontal/vertical timing for the standards you reach for when building a video controller in an FPGA: VGA and VESA, HDMI/DVI (CEA-861), analog broadcast (NTSC, PAL, SECAM), and the classic 8/16-bit machines.

The timing model

Every raster mode is one horizontal counter and one vertical counter. Each axis runs active → front porch → sync → back porch and wraps at its total. Horizontal counts pixel clocks; vertical counts whole lines. Blanking = front porch + sync + back porch. Sync polarity says whether the pulse drives the line low (negative, the VGA default) or high (positive). All porch figures below are in pixels (H) and lines (V) unless a unit is given.

Timing calculator

Enter the four porches per axis and the pixel clock. Get totals, line and frame rates, the counter compare points, and a paste-ready parameter block. The C64 and VIC-20 presets carry the right dot clock, totals, and line/frame rates; their porch split is nominal, since those chips draw borders and a composite sync rather than VGA porches.

Pixel clock (MHz)

H active (px)

H front porch

H sync

H back porch

H sync polarity

V active (lines)

V front porch

V sync

V back porch

V sync polarity

VGA & VESA

Progressive RGB modes with separate H and V sync, the usual target for FPGA VGA output through a resistor-ladder DAC. Pixel clock in MHz; H porches in pixels, V porches in lines.

Mode	Refresh	Pixel clock	Horizontal (px)					Vertical (lines)					Sync H / V	H freq	V freq
Mode	Refresh	Pixel clock	act	fp	sync	bp	total	act	fp	sync	bp	total	Sync H / V	H freq	V freq

Sync polarity: − active-low, + active-high. 720×400 @70 is the IBM VGA 80×25 text mode. 640×480 @60 lands on 59.94 Hz exactly (25.175 MHz), the one mode shared with CEA-861.

HDMI & DVI (CEA-861)

Digital TV formats. The same pixel timing feeds a DVI/HDMI TMDS serializer; HDMI just adds data islands during blanking. VIC is the CEA video identification code. Pixel clock in MHz.

VIC	Format	Pixel clock	Horizontal (px)					Vertical (lines)					Sync H / V	H freq	Rate
VIC	Format	Pixel clock	act	fp	sync	bp	total	act	fp	sync	bp	total	Sync H / V	H freq	Rate

Every NTSC-derived rate has a /1.001 sibling: drop the pixel clock to 25.175→(already 59.94), 27→26.973, 74.25→74.176, 148.5→148.352 MHz for the 59.94/29.97/23.976 Hz variants. 1080i vertical figures are per field; total 1125 lines carry 540 active each, sync/porch counted in half-lines.

Analog broadcast

Composite/component analog. These are scan parameters, not pixels: the line is a continuous waveform, so timing is in microseconds and levels in IRE or millivolts. Generating these from an FPGA means a fast video DAC and a precise subcarrier.

Parameter	NTSC-M	PAL-B/G	PAL-I	SECAM
Total lines / frame	525	625	625	625
Active lines (visible)	~480–486	576	576	576
Interlace	2:1	2:1	2:1	2:1
Fields / sec	59.94	50	50	50
Frames / sec	29.97	25	25	25
Line frequency f_H	15.734 kHz	15.625 kHz	15.625 kHz	15.625 kHz
Line period	63.556 µs	64.000 µs	64.000 µs	64.000 µs
Color subcarrier f_sc	3.579545 MHz	4.433619 MHz	4.433619 MHz	4.250 / 4.40625
Chroma encoding	QAM I/Q	QAM ±V	QAM ±V	FM sequential
Video bandwidth	4.2 MHz	5.0 MHz	5.5 MHz	6.0 MHz
Channel width	6 MHz	7 MHz	8 MHz	8 MHz
Sound offset	+4.5 MHz	+5.5 MHz	+6.0 MHz	+6.5 MHz
Black setup (pedestal)	7.5 IRE	0 IRE	0 IRE	0 IRE
Signal level (p-p)	1.0 V	1.0 V	1.0 V	1.0 V
Sync depth	−40 IRE (−286 mV)	−300 mV	−300 mV	−300 mV
Display gamma	2.2	2.8	2.8	2.8

NTSC f_H = 4.5 MHz ÷ 286 = 15734.264 Hz; f_sc = 315⁄88 MHz. PAL f_sc = (1135⁄4 + 1⁄625) × f_H. 1 IRE = 1⁄140 V = 7.143 mV across the 140-IRE sync-tip-to-white span.

One scan line, broken down (nominal values, ITU-R BT.470). The active window is where you clock out picture samples.

Horizontal interval	NTSC	PAL
Total line	63.556 µs	64.000 µs
Front porch	1.5 µs	1.65 µs
Sync pulse (low)	4.7 µs	4.7 µs
Back porch	4.5 µs	5.7 µs
Breezeway to burst	~0.6 µs	~0.9 µs
Color burst	2.5 µs (9 cyc)	2.25 µs (10 cyc)
Total H blanking	~10.9 µs	~12.05 µs
Active video	~52.6 µs	~51.95 µs

Vertical blanking carries the equalizing and serration pulses: 6 pre-equalizing (0.5H), the broad vertical sync (3 lines, serrated at 0.5H), then 6 post-equalizing pulses, before picture resumes near line 21 (NTSC) / line 23 (PAL).

Retro machine video

The 8 and 16-bit display chips, which is what you are usually re-creating on an FPGA. Dot clock is the pixel rate the chip shifts at; cycles/line counts in chip dots. Visible is the active picture inside the border.

Chip / system	Std	Master clock	Dot clock	CPU clock	Dots / line	Lines / frame	Visible	Frame
VIC-II (C64, 6567R8)	NTSC	14.31818 MHz	8.18182 MHz	1.022727 MHz	520	263	320×200	~59.83 Hz
VIC-II (C64, 6569)	PAL	17.734472 MHz	7.881984 MHz	0.985248 MHz	504	312	320×200	~50.12 Hz
PPU (NES, 2C02)	NTSC	21.477272 MHz	5.369318 MHz	1.789773 MHz	341	262	256×240	~60.10 Hz
PPU (NES, 2C07)	PAL	26.601712 MHz	5.320342 MHz	1.662607 MHz	341	312	256×240	~50.01 Hz
Agnus/Denise (Amiga OCS)	NTSC	28.63636 MHz	7.15909 MHz	7.15909 MHz	~455	262	320×200	~59.94 Hz
Agnus/Denise (Amiga OCS)	PAL	28.37516 MHz	7.09379 MHz	7.09379 MHz	~454	312	320×256	~50.08 Hz
ULA (ZX Spectrum 48K)	PAL	14.00 MHz	7.00 MHz	3.50 MHz	448	312	256×192	~50.08 Hz

Amiga lores dot is master⁄4 (hires doubles it to ~14.3/14.2 MHz); its line is measured in 3.5 MHz color clocks (227.5 NTSC / ~227 PAL), so dots/line are approximate. C64 NTSC uses 65 cycles/line (×8 dots), PAL 63. ZX Spectrum is 224 T-states/line at 3.5 MHz, 69888 T-states/frame.